IBM POWER4 seminar to be held on 1 October

Please join SCD Consulting Services for the following seminar:

"Hardware monitor for POWER4: Where is the performance?"

When: Wednesday, 1 October 2003 from 10:00–12:00.

Where: NCAR Mesa Laboratory, Main Seminar Room

Speaker: Bob Walkup, IBM

The POWER4 processor has counters for a number of events such as cache and TLB misses, instruction counts, clock cycles, etc. The counters are accessed using predefined event-groups via the performance-monitor API. The event-groups of interest will be discussed along with examples that illustrate what one can or cannot learn from the counter values; and the tools for monitoring single-process and MPI applications will be reviewed.