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Steve Oberlin from Cray Research delivered a general session talk on SGI/CRI hardware directions. A by-now familiar hardware evolution diagram was shown again that basically showed the T3E and
Origin 2000 converging to the Scalable Node 1 (SN1) architecture, then converging again with the T90 and J90 lines to the SN2. The SN1 is the first full SGI/CRI codesign. The SN2 is envisioned to come in two flavors: the "regular" SN2 will have a scalar/integer emphasis, while the SN2v will have a vector/floating-point emphasis. Each SN2 will be designed from the bottom up for its purpose; i.e., the SN2v will not be merely a souped-up SN2. In a departure from Cray's traditional insistence on simple, non-paged memory, it is anticipated that the SN2 will use a heirarchical memory system. The reason for this, it was explained, is that vector system performance has not kept up with Moore's Law, which postulates a doubling of performance every 18 months. The reason for this, it was further explained, is that IC density is improving faster than connectivity. |
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